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Lattice Semiconductor
Application Support
The main blocks and functions of the test application design are as follows:
The Test Logic Module
This module includes the address swap logic, loop back FIFO and associated control logic, and miscellaneous con-
trol and status glue logic between the MAC Rx/Tx Client interface and the register interface module.
The ORCAstra to Host Bus/USI module
This module converts the ORCAstra? bus (a Lattice defined slow speed serial bus) to the host bus and a user
slave interface bus. Using the ORCAstra bus, a user can access the internal TSMAC IP core registers, as well as
the test application registers. Note that external PHY registers can also be accessed via the ORCAstra interface
through the internal TSMAC IP core registers and the SMI interface in the TSMAC IP core. The MAC registers
(accessed via the host bus) and test logic registers (accessed via the USI) are memory mapped as described in
“Test Application Registers” on page 51 . An ORCAstra Bus Test bench driver is provided to ease simulation with
this interface.
The Register Interface Module
This module is accessed through the ORCAstra bus via the user slave interface (USI). The module contains regis-
ters used by the test application for control and status of the TSMAC IP core and external PHY. In addition this
module contains 16 bit statistics counters fed by the TSMAC IP core’s Rx/Tx statistics interfaces. These counters
can be read and cleared through the ORCAstra bus. An address map and description of these registers is given in
“Test Application Registers” on page 51 .
TSMAC Support Logic
This logic includes IO buffers, PLLs, clock dividers and multiplexers used by the TSMAC IP core and test applica-
tion. Use of technology-specific modules (like the I/O and PLLs) and their settings are pre-defined for this applica-
tion. They are based on the user configuration option selected. Information can be found in the downloaded files
(e.g. the _pll.v files in the models directory) that come with the IPexpress IP core installed package.
Simulation of the Test Application
Figure 5-2 shows a block diagram of the test bench setup provided with the Test Application Design. All Accesses
to the internal TSMAC registers and test application design registers can be accomplished through the testcase.v
file (via an Orcastra driver). In addition, variable size and types of ethernet frames can be sourced to the TSMAC
Rx G/MII port through the testcase.v file (via the Rx frame generator). These received packets get looped back
inside the test application design and are monitored on the TSMAC Tx G/MII port by a packet monitor. The moni-
tored packets are logged in a file named ethernet_pkts_sink. The testcase.v file can be found in
\< project_dir >\ts_mac_eval\testbench\tests . While the ethernet_pkts_sink file will be created and
placed in \< project_dir >\ts_mac_eval\tsmac\sim\(modelsim or aldec) directory once the simula-
tion is run and completed.
IPUG51_03.0, December 2010
49
Tri-Speed Ethernet MAC User’s Guide
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